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Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digital bipolar technology

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1 Author(s)
Razavi, B. ; AT&T Bell Labs., Holmdel, NJ, USA

This paper describes the design of an all-npn open-loop sample-and-hold amplifier intended for use at the front end of analog-to-digital converters. Configured as a quasidifferential topology, the circuit employs capacitive coupling between the input and output to achieve differential voltage swings of 3 V in a 3.3-V system. It also exploits the high speed of bipolar transistors to attain a sampling rate of 100 MHz with a power dissipation of 10 mW. A prototype fabricated in a 1.5-μm 12-GHz digital bipolar technology exhibits harmonics 60 dB below the fundamental with a 10-MHz sinusoidal input. The hold-mode feedthrough is less than -60 dB and the droop rate is 100 μV/ns

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 7 )

Date of Publication:

Jul 1995

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