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Chip-in-the-loop learning algorithm for Boltzmann machine

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3 Author(s)
Klein, J.O. ; Inst. d''Electron. Fondamentale, Univ. de Paris-Sud, Orsay, France ; Pujol, H. ; Garda, P.

A new algorithm is presented for chip-in-the-loop learning of the synchronous Boltzmann machine, which has two distinct advantages: it allows optimal use of analogue circuit dynamic range, unlike the conventional learning algorithm, and it features a coherent dual weight representation, which improves learning efficiency

Published in:

Electronics Letters  (Volume:31 ,  Issue: 12 )