By Topic

Design of concurrent error-detecting systolic arrays using |g 3N|M codes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Olivier, J.L. ; Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA ; Ozguner, F.

The problem of detection and identification of a faulty processing element in a systolic array is addressed. A method for designing processing elements with concurrent error detection is presented. The | gAN|M code is shown to be an effective code for encoding the operands in a systolic array. It is shown that the |g 3N|M code is equivalent to a residue code with the check and information bits interchanged, for an odd number of information bits. This allows arithmetic to be performed separately on the information and check bits while the output can be checked by an AN checker. An architecture and rules for designing a self-checking processing element (PE) for systolic arrays are presented. Both redundancy and extra delay of the self-checking PE are shown to be low

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:8 ,  Issue: 10 )