By Topic

An architecture for parallel interpretation: performance measurements

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Manwaring ; Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA ; M. Chowdhury ; V. Malbasa

An innovative architecture for parallel interpretation of high-level machine languages has been described by Manwaring et al. (1994). Performance measurements of the architecture, obtained by running representative benchmark programs on a cycle level simulator, are presented. The results show that a speed up of about two is achieved compared to the traditional sequential machine language interpretation on a single processor

Published in:

EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference.

Date of Conference:

5-8 Sep 1994