Design and performance evaluation of a parallel architecture for the Boltzmann machine

The Boltzmann Machine (BM) is a statistical neural model well suited to the approximate solution of combinatorial optimization problems and massively parallel implementations. In this paper we present a dedicated parallel architecture for the BM, organized as an array of processing elements (PEs) that communicate with a host workstation through a linear shared bus. Each PE contains a low-cost general purpose processor (MC68000), local memory, synchronization and initialization hardware. The host executes the sequential part of the BM procedure and drives the processor array through a fork-join mechanism to start the parallel routines. The paper shows a set of measurements on a first prototype and demonstrates interesting speedup/cost figures with respect to state-of-the-art workstations when attacking large optimization problems with a proper number of PEs.<
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