By Topic

Characterization and design of GaAs SCFL latched comparators based on improved linearized models

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Feng, S. ; Fraunhofer Inst. for Integrated Circuits, Erlangen, Germany ; Seitzer, Dieter

This brief presents characterization and design considerations of high-speed and high-precision GaAs latched comparators consisting of source coupled FET logic (SCFL) flip flops. In order to characterize the comparators, linearized equivalent circuit models are improved for the SCFL flip flops. Based on the models, critical design parameters such as recovery time, regeneration time and input voltage sensitivity are determined for the comparators. Circuit configurations for increasing circuit speed and accuracy are characterized and compared. One comparator is optimized and implemented in a 0.5 μm GaAs E/D HEMT technology. Measurement results demonstrate the implemented comparator achieves an average voltage sensitivity of 11.5 mV at low frequencies and an optimal voltage sensitivity of 10.0 mV at an input signal frequency of 2 GHz and a clock frequency of 4 GHz. Predicted voltage sensitivities are also verified to be in good agreement with the measured results

Published in:

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:42 ,  Issue: 6 )