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Optimal VLSI architecture for distributed arithmetic-based algorithms

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2 Author(s)
K. Nourji ; Telecom Paris, Ecole Nat. Superieure des Telecommun., Paris, France ; N. Demassieux

Digital signal processing algorithms often use inner product as basic computation. In this paper we propose a new design methodology for synthesizing an optimal VLSI architecture implementing a real-time Distributed Arithmetic-based inner product. Our design methodology considers the design space as bidimensional one. In the first dimension we consider all possible input data parallelisations: from bit-serial to bit-parallel. In the second dimension we consider all possible lookup-table partitioning. Using a new ROM generic model, expressions are developed for area and maximum input data bandwidth, which allows to have an explicit formulation of the area-bandwidth tradeoff. Finally, for a given set of application constraints (inner product size and data bandwidth), we exhibit the optimal architectural parameters that provide the smallest chip area

Published in:

Acoustics, Speech, and Signal Processing, 1994. ICASSP-94., 1994 IEEE International Conference on  (Volume:ii )

Date of Conference:

19-22 Apr 1994