Close category search window
 

Delay-shared N-path structures for video-rate SC FIR filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Cortelazzo, G.M. ; Dipartimento di Elettronica e Inf., Padova Univ., Italy ; Malavasi, E. ; Segato, M. ; Baschirotto, A.

Switched-capacitor technology implemented by 2.4 μm CMOS offers considerable reliability/cost advantages. Its limited clock-rate values are the traditional obstacle to its introduction in high frequency applications, such as video. This obstacle can be removed by an architectural scheme broadening the internal clock rate by an integer factor with respect to the input clock rate. The feasibility of this concept is demonstrated by the switched-capacitor realization of a color difference prefilter complying with Recommendation CCIR 601

Published in:
Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:5 ,  Issue: 2 )

Date of Publication: Apr 1995

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.