Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's

This paper proposes one-dimensional spacing algorithms that minimize [maximize] the degree of separation [proximity] among the specified elements of a given integrated circuit layout. Number of problems on chip and MCM systems such as poor performance, higher crosstalk, lower yield etc. are related to the degree of separation [proximity]. The proposed algorithms utilize the attractive [repulsive] constraints to shrink [expand] the distances among the specified elements while keeping the layout free of any design rule errors. The spacing problem is reduced to a parametric linear programming problem and a network simplex algorithm is proposed for solving it. The proposed algorithms are implemented into a system called PERFECT for performance enhancement and crosstalk reduction. Given a routed design, PERFECT minimizes delay due to the coupled capacitance, which could contribute as much as 50-75% to the interconnect delay in near future. PERFECT utilizes the repulsive constraints between interconnect segments for the purpose. The experimental results show a significant delay improvement and the crosstalk reduction for submicron technologies.<
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