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A monolithic Hough transform processor based on restructurable VLSI

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6 Author(s)
F. M. Rhodes ; MIT Lincoln Lab., Lexington, MA, USA ; J. J. Dituri ; G. H. Chapman ; B. E. Emerson
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The implementation of a Hough transform processor using a wafer-scale-integration technology, restructurable VLSI circuit is described. The Hough transform is typically used as a grouping operation in an image processing sequence. The transform discussed here groups pixels in order to extract linear features. This calculation is realized with a wafer-scale processor that allows a complete line extraction system to be integrated on a single PC board. Also discussed is the use of the CAD tools that allowed this processor to be realized without incurring silicon layout and processing overhead

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IEEE Transactions on Pattern Analysis and Machine Intelligence  (Volume:10 ,  Issue: 1 )