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A compact low noise operational amplifier for a 1.2 μm digital CMOS technology

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2 Author(s)
Holman, W.T. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Connelly, J.A.

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 μm digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral β. The fabricated op amp has an area of only 0.211 mm2 with En=3.2 nV/√(Hz), In=0.73 pA/√(Hz), En and In 1/f noise corner frequencies less than 100 Hz, a -3 dB bandwidth greater than 10 MHz with a closed loop gain of 20.8 dB, a minimum PSRR (DC) of 68 dB, a CMRR (DC) of 100 dB, a minimum output slew rate of 39 V/μs, and a quiescent current of 2.1 mA at supply voltages of ±2.5 V. The operational amplifier drives a 1 kΩ resistive load to 1 V peak-to-peak at 10 MHz and has been used as a versatile building block for mixed-signal IC designs

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 6 )

Date of Publication:

Jun 1995

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