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Fine-grain multi-thread processor architecture for massively parallel processing

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4 Author(s)
Kawano, T. ; Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan ; Kusakabe, S. ; Taniguchi, R.-I. ; Amamiya, M.

Latency, caused by remote memory access and remote procedure call, is one of the most serious problems in massively parallel computers. In order to eliminate the processors' idle time caused by these latencies, processors must perform fast context switching among fine-grain concurrent processes. In this paper, we propose a processor architecture, called Datarol-II, that promotes efficient fine-grain multi-thread execution by performing fast context switching among fine-grain concurrent processes. In the Datarol-II processor, an implicit register load/store mechanism is embedded in the execution pipeline in order to reduce memory access overhead caused by context switching. In order to reduce local memory access latency, a two-level hierarchical memory system and a load control mechanism are also introduced. We describe the Datarol-II processor architecture, and show its evaluation results

Published in:

High-Performance Computer Architecture, 1995. Proceedings., First IEEE Symposium on

Date of Conference:

1995