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Massively parallel array processor for logic, fault, and design error simulation

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5 Author(s)
Hur, Y.-M. ; ECE Dept., Texas Univ., Austin, TX, USA ; Szygenda, S.A. ; Scott Fehr, E. ; Ott, G.E.
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Digital logic, fault, and error simulation of large VLSI circuits is one of the most compute-intensive tasks in digital systems analysis. This paper describes a massively parallel special purpose array processor, or hardware accelerator, for digital logic, fault, and error simulation. Hardware simulation is a viable approach for simulation of large systems, since simulation time increases rapidly as a function of the size and complexity of the systems to be simulated. In order to reduce the cost and to achieve high performance, a massively parallel array processor and new algorithms have been introduced. By executing an efficient and direct model of the design on the PE array, the architecture can provide high performance, similar to prototyping. Simulation results show that the hardware accelerator is orders of magnitude faster than software simulation

Published in:

High-Performance Computer Architecture, 1995. Proceedings., First IEEE Symposium on

Date of Conference:

1995