By Topic

1993 European Conference on Design Automation with the European Event in ASIC Design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

The following topics are dealt with: logic and circuit simulation methods; floorplans and global routing; design system integration; CAD systems for high-level design; design verification and Boolean matching; formal methods in design; new directions in routing; design for testability; high-level testing; placement; synthesis and optimization of sequential circuits; built-in self test; mixed digital analog designs; representations and manipulations of Boolean functions; interconnect issues in high-level synthesis; technology mapping; emerging issues in design systems; power estimation; multilevel combinational synthesis; scheduling algorithms and storage synthesis; layout analysis and optimization; fault simulation and testability measures; new algorithms for timing analysis; application-specific CAD advances in test-pattern generation; asynchronous design techniques; architecture of digital systems; new approaches in data path synthesis; and layout-driven synthesis

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb. 1993