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An integrated approach to pin assignment and global routing for VLSI building-block layout

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3 Author(s)
Koide, T. ; Fac. of Eng., Hiroshima Univ., Kagamiyama, Higashi-Hiroshima, Japan ; Wakabayashi, S. ; Yoshida, N.

An efficient algorithm integrating global routing, pin assignment, block reshaping and positioning, which is based on a rip-up and reroute and the simulated evolution technique, is presented. Experimental results show that the proposed algorithm achieves up to 10.5% reduction of chip area and up to 34.6% reduction of total wire length compared with previous methods

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993