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Functional verification for retiming and rebuffering optimization

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2 Author(s)
Kostelijk, A.P. ; Philips Res. Lab., Eindhoven, Netherlands ; van der Werf, A.

An algorithm which proves or disproves functional consistency of a sequential datapath after a combination of retiming, pipelining and buffering optimizations is presented. The verification algorithm is complete and efficient. It includes verification of external latency constraints. Experiments have confirmed the speed of the implemented algorithm and errors were clearly indicated in industrial designs

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993