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Partial reset: An inexpensive design for testability approach

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2 Author(s)
B. Mathew ; Coordinated Sci. Lab., Univ. of Illinois, Urbana, IL, USA ; D. G. Saab

A design for testability (DFT) method called partial reset is studied. Reset lines are added to a subset of the flip-flops. partial reset improves the fault coverage of sequential circuit, on the average, by 15% over the fault coverage of the original circuit. This approach has lower overhead in terms of test application time and hardware area when compared to scan techniques. This method has been tested on the 1989 ISCAS sequential benchmark circuits and favorable results have been obtained

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993