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RT-level transformations for gate-level testability

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3 Author(s)
Bhattacharya, S. ; Dept. of Comput. Sci., Duke Univ., Durham, NC, USA ; Dey, S. ; Brglez, F.

The authors introduce a technique to transform a given RT-level design into a functionality equivalent, minimized design which is 100% testable under full-scan at the gate level. The proposed optimization technique uses the RT-level structure and exploits the interaction between the control and the data path. The approach maintains the design hierarchy while performing RT-level transformations of initially specified data path, followed by resynthesis of control using do not cares extracted from the data path. Experiments with RTL benchmarks demonstrate the effectiveness of the technique in generating fully testable designs, while consistently reducing area and delay

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993

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