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Browse Conference Publications > Design Automation, 1993, with ... Help

High level testability analysis using VHDL descriptions

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2 Author(s)
Vishakantaiah, P. ; Comput Eng. Res. Center, Univ. of Texas, Austin, TX, USA ; Abraham, J.A.

Tests generated for modules in a design may not be applicable from the design boundaries due to global constraints. The authors discuss high level techniques that can be used to analyze a sequential circuit and precompute useful information that reflects the controllability of inputs and observability of outputs of modules in the design. The information can then be used in conjunction with the tests generated for modules to obtain high quality tests for the design quickly. Results obtained for example circuits are presented to demonstrate the techniques

Published in:
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference: 22-25 Feb 1993

Page(s):
170 - 174
Meeting Date :
22 Feb 1993-25 Feb 1993
Print ISBN:
0-8186-3410-3
INSPEC Accession Number:
4885165
Conference Location :
Paris
Digital Object Identifier :
10.1109/EDAC.1993.386481

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