By Topic

Restructuring of synchronous logic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Bill Lin ; IMEC Lab., Leuven, Belgium

Circuit decomposition techniques for global restructuring of synchronous digital circuits across register boundaries are presented. Circuit decomposition involves finding common sub-expressions that can be shared across the entire design. It is well-known that circuit decomposition has a substantial impact on circuit size reduction. The problem of finding a right circuit decomposition is a difficult one because a circuit can be decomposed in many ways. In the case of synchronous circuits, the problem is complicated by the fact that registers can be moved. Finding a good set of common divisors that can be extracted simultaneously requires a careful orchestration of register movements and function decompositions. This is difficult to achieve without a global view. Novel techniques using the concepts of synchronous kernels and kernel intersections are proposed for finding common (multiple cube) divisors in synchronous logic circuits that considers implicitly retiming. Preliminary results on synchronous benchmarks demonstrate the feasibility of the approach

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993