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A CMOS clock-frame regeneration chip with ECL-compatible input/output [for SONET]

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5 Author(s)

The IC is a mixed analog/digital circuit performing the clock regeneration and frame recovery for SONET applications. The clock regeneration is realized by an analog approach, while the frame recovery is implemented using digital techniques. ECL-CMOS and CMOS-ECL converters are designed to keep the maximum peak clock jitter lower than 300 ps and the RMS jitter below 70 ps. New frame detection technique is used to relax the speed requirement on the digital part of the circuit. The chip is fabricated in a 1.2-μm-CMOS process measuring a 35-mm2 silicon area. The chip is powered by as single 5-V supply and is capable of handling signals up to 180 MHz

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993