By Topic

A novel interpolator architecture for ΣΔ DACs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Francesconi, F. ; Dept. of Electron., Univ. of Pavia, Italy ; Lazzari, G. ; Liberali, V. ; Maloberti, F.
more authors

A scheme to implement Lagrange interpolation for Σ-Δ D/A (digital/analog) converters is presented. The proposed implementation requires only sums of digital signals, avoiding the use of generic multipliers. The circuit has a reduced complexity and is suitable for very high-frequency operation. The given analysis shows that the presented architecture has good performance both in the passband and in the stopband. The effects of finite digital word length are also discussed

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993