A novel interpolator architecture for /spl Sigma//spl Delta/ DACs

A scheme to implement Lagrange interpolation for /spl Sigma/-/spl Delta/ D/A (digital/analog) converters is presented. The proposed implementation requires only sums of digital signals, avoiding the use of generic multipliers. The circuit has a reduced complexity and is suitable for very high-frequency operation. The given analysis shows that the presented architecture has good performance both in the passband and in the stopband. The effects of finite digital word length are also discussed.<
>