By Topic

Fast technology mapping for multiplexor-based architecture with area/delay tradeoff

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Hermann ; Dept. of Electr. Eng., Tech. Univ. of Munich, Germany ; U. Schlichtmann ; K. J. Antreich

The authors present enhancements for a BDD-based approach to mapping Boolean networks multiplexor-based architectures like a FPGA by Actel. The algorithm combines the following: transformation of the Boolean network into a mixed BDD/ITE-description, an area-delay tradeoff and effective tree-pruning using a large library. The algorithm performs several times faster than state-of-the-art approaches while delivering competitive results. Its intended usage is the frequent evaluation of the necessary chip area for a given set of Boolean functions in a logic minimization tool

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993