Cart (Loading....) | Create Account
Close category search window
 

Simulation and reduction of CMOS power dissipation at logic level

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Dresig, F. ; Tech. Univ. of Chemnitz, Germany ; Lanches, P. ; Rettig, O. ; Baitinger, U.G.

A logic simulation approach suitable to get information about the dissipated power of a system without the need of a specific current simulation is described. With this approach it is possible to retrieve estimations for average power dissipation under typical operating conditions. Furthermore a mapping approach which performs a power-minimal mapping for a given CMOS combinational circuit structure is suggested

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.