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Simulation and reduction of CMOS power dissipation at logic level

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4 Author(s)
Dresig, F. ; Tech. Univ. of Chemnitz, Germany ; Lanches, P. ; Rettig, O. ; Baitinger, U.G.

A logic simulation approach suitable to get information about the dissipated power of a system without the need of a specific current simulation is described. With this approach it is possible to retrieve estimations for average power dissipation under typical operating conditions. Furthermore a mapping approach which performs a power-minimal mapping for a given CMOS combinational circuit structure is suggested

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993