By Topic

Circuit activity driven multilevel logic optimization for low power reliable operation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Prasad, S.C. ; Integrated Syst. Lab. Texas Instruments Inc., Dallas, TX, USA ; Roy, K.

The problem of optimization of multilevel combinational logic to achieve low power dissipation as well as low area is considered wherein it is assumed that static CMOS gates are used. Given a multilevel Boolean network as a collection of functions, the system determines a new function at a time, adds it to the collection and expresses the existing functions in terms of it. In selecting the new function the effect on power dissipation as well as area are considered. The authors describe an efficient implementation of a general algorithm to compute expected number of transitions per unit time at circuit nodes. These numbers are in turn used to compute power dissipation. A prototype multilevel logic optimization system has been implemented. Results are given for a selection of benchmark examples

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993