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Using circuit hierarchy for fault simulation in combinational and sequential circuits

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3 Author(s)
H. C. Wittmann ; Dept. of Electr. Eng., Tech. Univ. of Munich, Germany ; B. H. Seiss ; K. J. Antreich

Several concepts for exploiting the hierarchy in circuit description during the fault simulation of combinational and sequential circuits are introduced. The impact of these concepts on the single steps of fault simulation based upon single fault propagation and parallel pattern single fault propagation technique is discussed. An algorithm for the fault simulation of hierarchical circuits based upon parallel pattern single fault propagation in combination with the extended concept of fanout free regions is presented. The algorithm makes use of all of the concepts. Experimental results with industrial circuits with up to five levels of hierarchy and up to 90,000 gates demonstrate the advantages of the hierarchical fault simulator in terms of CPU-time consumption and memory requirements as compared to a fast gate level fault simulator

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993