By Topic

Technology decomposition using optimal alphabetic trees

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Pedram, M. ; Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA ; Vaishnav, H.

A technique for converting an arbitrary sum-of-products expression into a subnetwork of two-input NAND gates such that, given a fixed linear order on the inputs to the expression, the signal arrival time at the output of the subnetwork is minimum, is presented. The procedure, which is based on an algorithm for constructing optimal binary trees for alphabetic codes, is optimal for complex nodes with sum-of-products expressions having noncrossing literal support. This procedure has been said to recursively NAND-decompose a Boolean network based on the input ordering information derived from a companion placement solution resulting in reduced chip area and improved performance after technology mapping, placement and routing

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993