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An ASIC macro cell multiplier for complex numbers

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3 Author(s)
Soulas, T. ; Ecole Superieure d''Ingenieurs en Electrotech. et Electron., Noisy le Grand, France ; Villeger, D. ; Oklobdzija, V.G.

An architecture for ASIC macro cell implementing a complex number multiplier with applications in a digital signal processing ASIC chip is described. The complex numbers are packed into one 32-bit word. The design is unique and combines shared Booth encoding for the real and imaginary parts including only one combined modified Wallace tree. The regular Wallace tree and the tree of 4:2 adders for the complex multiplier implementation are compared. The authors took advantage of 4:2 adders in implementing the combined bit compression tree for each part. This design resulted in a more compact wiring structure and balanced delays resulting in faster multiplier circuit. The number of adders was also decreased

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993

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