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VLSI architectures for the discrete wavelet transform

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3 Author(s)
Vishwanath, M. ; Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA ; Owens, Robert Michael ; Irwin, M.J.

A class of VLSI architectures based on linear systolic arrays, for computing the 1-D Discrete Wavelet Transform (DWT), is presented. The various architectures of this class differ only in the design of their routing networks, which could be systolic, semisystolic, or RAM-based. These architectures compute the Recursive Pyramid Algorithm, which is a reformulation of Mallat's pyramid algorithm for the DWT. The DWT is computed in real time (running DWT), using just Nw(J-1) cells of storage, where Nw is the length of the filter and J is the number of octaves. They are ideally suited for single-chip implementation due to their practical I/O rate, small storage, and regularity. The N-point 1-D DWT is computed in 2N cycles. The period can be reduced to N cycles by using Nw extra MAC's. Our architectures are shown to be optimal in both computation time and in area. A utilization of 100% is achieved for the linear array. Extensions of our architecture for computing the M-band DWT are discussed. Also, two architectures for computing the 2-D DWT (separable case) are discussed. One of these architectures, based on a combination of systolic and parallel filters, computes the N2-point 2-D DWT, in real time, in N2+N cycles, using 2NNw cells of storage

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:42 ,  Issue: 5 )