A scalable high-speed current-mode winner-take-all network for VLSI neural applications

This paper describes a very flexible, high-speed current-mode winner-take-all network (WTA) for use in artificial neural systems. Since the WTA is based on a network of identical current switching cells requiring only adjacent transistor matching, it is particularly suited to use in large systems. In addition, since the network is based on a tree structure, very little space is occupied by interconnect, thus ensuring a very compact layout. This WTA has current (matching score) inputs and provides a buffered, binary encoded voltage output.<
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