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Single clock partial scan

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1 Author(s)
Kwang-Ting Cheng ; California Univ., Santa Barbara, CA, USA

Existing partial-scan designs use a separate scan clock to simplify scan flip-flop selection and test generation methods. Such designs require multiple clock trees and create clock-signal routing problems that, in general, require tight control of clock skew. The author examines using the system clock for the scan operation and includes experimental results based on ISCAS89 benchmark circuits

Published in:

Design & Test of Computers, IEEE  (Volume:12 ,  Issue: 2 )

Date of Publication:

Summer 1995

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