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Fast-acquisition PLL synthesizer using a parallel N-stage cycle swallower with low power consumption and low phase noise

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3 Author(s)
Saba, T. ; Dept. of Electr. Eng., Keio Univ., Yokohama, Japan ; Duk-Kyu Park ; Mori, S.

A phase-locked loop (PLL) frequency synthesizer with an N-stage cycle swallower (NSCS) is one of the fastest frequency switching synthesizers, but the use of the NSCS results in high power consumption and phase noise in the UHF band. This paper elucidates these problems and proposes a fast-acquisition PLL synthesizer using a novel type of NSCS with low power consumption and low phase noise. Experimental results confirm that the use of a parallel NSCS and a prescalar results in greatly reduced power consumption and phase noise

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Vehicular Technology, IEEE Transactions on  (Volume:44 ,  Issue: 2 )