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Path-delay-fault testable nonscan sequential circuits

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2 Author(s)
Ke, W. ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; Menon, P.R.

In this paper we show that any finite state machine can be implemented by a fully path-delay-fault testable nonscan sequential circuit. Synthesis methods are proposed, which use a one-hot encoding of states, a special circuit structure and at most one additional input. Combined with existing synthesis techniques for delay-fault testable combinational circuits, these methods can produce nonscan sequential circuits in which every path has a robust or validatable nonrobust test

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:14 ,  Issue: 5 )