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Test embedding with discrete logarithms

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3 Author(s)
M. Lempel ; LSI Logic Corp., Milpitas, CA, USA ; S. K. Gupta ; M. A. Breuer

When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probability of detecting the fault having the fewest test patterns. We then show how to guide the search for an initial state (seed) for a LFSR with a given primitive feedback polynomial so that all the faults of interest are detected by a minimum length test sequence. Our algorithm is based on finding the location of test patterns in the sequence generated by this LPSR. This is accomplished using, the theory of discrete logarithms. We then select the shortest subsequence that includes test patterns for all the faults of interest, hence resulting in 100% fault coverage

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:14 ,  Issue: 5 )