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A static power saving TTL-to-CMOS input buffer

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3 Author(s)
Changsik Yoo ; Dept. of Electron. Eng., Seoul Nat. Univ., South Korea ; Min-Kyu Kim ; Kim, Wonchan

This paper describes a TTL-to-CMOS input buffer that has no static power consumption for the typical TTL voltage level. The input buffer utilizes a feedback configuration to eliminate static power consumption that renders hysteresis characteristic. The hysteresis characteristic is equivalent to that of a Schmitt trigger and thus provides good noise immunity. A prototype circuit was implemented in a 0.8 μm CMOS process, and the through current is measured to be only 8.9 μA and 11.7 μA for the input of 0.8 V and 2.2 V (the worst case TTL level), respectively. The input buffer gives full-swing output upto 170 MHz when driving a minimum sized inverter with the worst case TTL level according to SPICE simulation

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 5 )