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Glitch reduction in second-generation SI circuits

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2 Author(s)
Oliaei, O. ; Electron. Dept., Ecole Nat. Superieure des Telecommun., Paris, France ; Loumeau, P.

A simple method for reducing the glitches of second-generation SI circuits is presented. For a given SI circuit it is sufficient to apply this technique only to the last stage

Published in:

Electronics Letters  (Volume:31 ,  Issue: 8 )