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Pass transistor designs using pocket implant to improve manufacturability for 256 Mbit DRAM and beyond

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6 Author(s)
A. Chatterjee ; Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA ; J. Liu ; S. Aur ; P. K. Mozumder
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Pass transistor designs for scaled 256 Mbit DRAM are studied in this paper. It is shown, for the first time, that a L/sub g/=0.25 /spl mu/m and t/sub ox/=85 /spl Aring/ transistor utilizing a pocket implant together with a light V/sub TN/ implant (pocket-with-V/sub TN/) can satisfy the stringent requirements of subthreshold leakage, diode leakage, V/sub T/ during charging, and a tolerance for L/sub g/ variation of 0.08 /spl mu/m for manufacturability. The success of the pocket-implant device in meeting the above design spec is due to the reduced V/sub T/ roll-off at shorter L/sub g/ and reduced body effect at longer L/sub g/ compared to those of a conventional device. An optimum range of substrate bias is determined to be -1.5 to -2 V. It is also shown that the pocket implant does not degrade the gate oxide integrity nor channel hot-electron reliability.<>

Published in:

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Date of Conference:

11-14 Dec. 1994