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Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies

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2 Author(s)
S. H. Voldman ; Microelectron. Div., IBM Corp., Essex Junction, VT, USA ; G. Gerosa

Optimization of a 3.3-V/ 5.0-V tolerant electrostatic discharge (ESD) protection network for both diffused n-well/LOCOS and retrograde well/shallow trench isolation (STI) CMOS technologies in a RISC microprocessor is discussed. ESD-related semiconductor-process key design features, ESD circuit operation, data, simulation and failure analysis are presented. ESD robustness of 4000-V human body model (HBM), 400-V machine model (MM), and 1500-V charge device model (CDM) is achieved in both technologies using a common design.<>

Published in:

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Date of Conference:

11-14 Dec. 1994