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Dual polycide gate and dual buried contact technologies achieving a 0.4 /spl mu/m nMOS/pMOS spacing for a 7.65 /spl mu/m/sup 2/ full-CMOS SRAM cell

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5 Author(s)
Koike, H. ; Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan ; Unno, Y. ; Ishimaru, K. ; Matsuoka, F.
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An enlarged grain dual polycide gate and a dual buried contact technology using regrown amorphous-Si have been developed for high density full-CMOS SRAM cell. Lateral dopant diffusion has been suppressed to be less than 0.2 /spl mu/m, as a result, 0.4 /spl mu/m nMOS/pMOS spacing was realized using an 850/spl deg/C process. This technology can also achieve dual buried contact with low resistance and suppress gate depletion simultaneously. A 7.65 /spl mu/m/sup 2/ full-CMOS cell using 0.35 /spl mu/m design rule has been realized and superior cell stability at 1.5 V operation has been confirmed.<>

Published in:

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Date of Conference:

11-14 Dec. 1994