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Designing efficient parallel algorithms on CRAP

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4 Author(s)
Tzong-Wann Kao ; Dept. of Electr. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan ; Shi-Jinn Horng ; Yue-Li Wang ; Horng-Ren Tsai

A cross-bridge reconfigurable array of processors is a parallel processing system which has the ability to change dynamically the supported interconnection scheme during the execution of an algorithm. Based on this architecture, several O(1) time basic operations such as the transpose, the untranspose, the shift, the unshift and the prefix sum of a binary sequence are first proposed. Then, these basic operations can be used to find the kth smallest element of N m bits unsigned integers in O(m) time using N processors and to sort N data items in O(1) time using O(N5/3) processors instead of using O(N2) processors as those proposed by other researchers

Published in:

Parallel and Distributed Systems, IEEE Transactions on  (Volume:6 ,  Issue: 5 )