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Browse Journals & Magazines > Computers, IEEE Transactions ...> Volume:44 Issue:5 Help

Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits

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3 Author(s)
Thibeault, C. ; Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada ; Savaria, Y. ; Houle, J.-L.

In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in Koren and Stapper (1989); one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy

Published in:
Computers, IEEE Transactions on  (Volume:44 ,  Issue: 5 )

Date of Publication: May 1995

Page(s):
724 - 728
ISSN :
0018-9340
INSPEC Accession Number:
4969409
Digital Object Identifier :
10.1109/12.381962
Product Type:
Journals & Magazines
Date of Current Version :
06 August 2002
Issue Date :
May 1995
Sponsored by :
IEEE Computer Society

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