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Performance analysis and optimal system configuration of hierarchical two-level COMA multiprocessors

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2 Author(s)
Ting-Li Hu ; Dept. of Electr. Eng., Akron Univ., OH, USA ; Sibai, F.N.

The single-bus UMA architecture with the write-once cache protocol is a simple and popular choice, however, it only works well for multiprocessors with tens of processors. For larger multiprocessors, the hierarchical COMA architecture provides excellent scalability while very well maintaining the system performance. This paper analyzes the performance of hierarchical 2-level COMA multiprocessors based on the write-once cache protocol using the modified MVA model and assuming a uniform request distribution. The results show that the hierarchical 2-level COMA architecture call support hundreds of clusters of minimal COMAs without much degradation of system performance. The trends in optimal system configurations, optimal efficiencies, and optimal speedups of 2-level COMA are also analyzed in the paper for various cache line and data sharing percentage settings

Published in:

Frontiers of Massively Parallel Computation, 1995. Proceedings. Frontiers '95., Fifth Symposium on the

Date of Conference:

6-9 Feb 1995

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