The iterative collapse algorithm: a novel approach for the design of long constraint length Viterbi decoders. I

The paper addresses in depth the system tradeoff issues of the VLSI implementation of long constraint length and/or high rate Viterbi decoders (VDs) and presents the iterative collapse algorithm (ICA) for the systematic generation of parallel architectures for the VD. The ICA is a specific form of partitioning the trellis diagram of the encoder using its inherent symmetries and permits the optimal down scaling of the design to the point where a single-chip VD is feasible. The effectiveness of the ICA is demonstrated by obtaining better than linear tradeoff between throughput and complexity for a wide range of complexity reduction factors. The existence of isomorphic topologies for the VDs associated with encoders having different memories derived through the application of the ICA permits the design of programmable decoders. Programmable decoders in turn can be used in a portable communication environment to provide power control for the portable transceiver depending on the channel state and the required data rate. The feasibility of the design of single-chip VDs leads to a significant power saving in comparison to the multi-chip design option