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CMOS technology for low voltage/low power applications

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3 Author(s)
Davari, B. ; Semicond. Res. & Dev. Center, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Dennard, R.H. ; Shahidi, G.G.

In this paper, the scaled CMOS as the ideal technology for the low power revolution, is discussed. It is shown that by the proper scaling of the CMOS devices, improved performance, power, and density can be achieved SIMULTANEOUSLY. The above scaling is made possible by; the reduction of the supply voltage, and the improved manufacturing tolerances and minimum dimensions. The reduction of the supply voltage is needed to lower the power dissipation per device and to maintain adequate reliability at improved performance. The CMOS technologies ranging from 0.25 μm CMOS @ 2.5 V down to 0/1 μm @ 1.XV on bulk and SOI (Silicon On Insulator) are presented. Over two orders of magnitude improvement in power x delay (mW/MIPS) is expected by the scaling of CMOS down to the 0.1 μm (Leff) regime

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994