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High performance 3.3 and 5 volt 0.5-μm CMOS technologies for ASICs

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14 Author(s)
Kizilyalli, I.C. ; AT&T Bell Labs., Allentown, PA, USA ; Thoma, M.J. ; Lytle, S.A. ; Martin, E.P.
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Two manufacturable high performance 0.5 pm CMOS technologies, one optimized for 5 V operation and the second optimized for 3.3 V operation, are presented. An improvement of 2 in circuit performance, 3.4 in packing density, 1.5 and 3.2 (for 5 and 3.3 V) in power consumption at constant speed, and 1.45 (for 3.3 V) in power consumption at maximum speed is achieved over AT&T's previous generation 0.9 μm CMOS technology by device scaling, and aggressive interconnect and isolation design rules

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994

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