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RRANN: the run-time reconfiguration artificial neural network

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2 Author(s)
J. G. Eldredge ; Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA ; B. L. Hutchings

Run-time reconfiguration is a way of more fully exploiting the flexibility of reconfigurable field programmable gate arrays (FPGAs). The run-time reconfiguration artificial neural network (RRANN) uses runtime reconfiguration to increase the hardware density of FPGAs. This is done by dividing the backpropagation algorithm into three sequentially executed stages and configuring the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single FPGA can implement by 500%. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994