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A 1.2 GIP general purpose digital image processor

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5 Author(s)
Evans, S. ; Dept. of Electron. & Electr. Eng., Sheffield Univ., UK ; Walker, S. ; Thacker, N.A. ; Yates, R.B.
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In this paper we present a new processor (DIP chip) for image compression which combines principles of multi-pipeline and array processing. The device is not specific to any one image compression algorithm, and can be regarded as a general purpose processor. The main aim of this paper is to describe our solutions to problems associated with the large bandwidth required, for both image data and instruction streams. We also address the necessary problem of increasing the array clock frequency relative to the input/output clock frequency without the need for a large on chip instruction cache, or fast external clock speeds

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994