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An 180 MHz 16 bit multiplier using asynchronous logic design techniques

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3 Author(s)
Burford, R.G. ; Joint Res. Centre in Inf. Technol., Flinders Univ., Adelaide, SA, Australia ; Fan, X. ; Bergmann, N.W.

A CMOS digital logic design technique is described which exploits the advantages of fast precharged logic and efficient latch design commonly used in synchronous systems while maintaining the features of localized control inherent in asynchronous design. A pipelined sixteen bit multiplier is presented and its performance compared with several previously reported asynchronous and synchronous designs

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994

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