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IDDQ testing on a custom automotive IC

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2 Author(s)
Mallarapu, S.R. ; Delco Electron. Corp., Kokomo, IN, USA ; Hoffman, A.J.

This paper presents the impact of quiescent current (IDDQ ) test on the fallout of a CMOS custom automotive IC designed to perform IDDQ tests, IDDQ patterns developed for this IC, together with the fault-graded patterns, achieved significantly higher fault coverage compared to the conventional Single Stuck-at-Fault (SAF) approach alone. We will show how the IC was designed to accommodate IDDQ testing, how the IDDQ faults were targeted and detected and analyze how it contributed to the reliability of the part. Setting the limits for the quiescent current and the impact of a voltage screen on these tests have also been presented

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994